Recently, with the high speed operation of a microprocessor, a synchronous DRAM (SDRAM) has been used to input/output data in synchronization with an external clock signal. However, since a DRAM does not operate with enough speed in some instances for the microprocessor, synchronization operation is applied in order to improve the performance of the DRAM by reducing the speed gap between the DRAM and the microprocessor.
In the synchronous DRAM (SDRAM), the data are input and output using an internal clock signal which is produced in synchronization with an external clock signal. Since this synchronous DRAM (SDRAM) executes the data input/output operations based on the internal clock signal, it is possible to write and read out the data in high speed.
Meanwhile, in the synchronous DRAM device, it is important to secure normal setup/hold time for an internal clock signal in order to normally write and read out the data. Here, the setup time means an amount of time data input must be applied before an external clock signal is issued and the hold time means an amount of time the input data must be maintained after the external clock signal is issued. That is, the setup time means an amount of time taken prior to start of a data valid window and the hold time means an amount of time taken after the data valid window.
A conventional measurement of the data setup/hold time is executed by changing a delay section between an input data and a clock signal in external equipment and then comparing the input data with an output data from an output pad through read/write operations.
However, this conventional measurement of the setup/hold time needs the external equipment to change the delay section between the data input and the clock signal and deteriorates the efficiency because the read/write operations must be executed to compare the input data with the output data from the pad.